The present invention relates to a semiconductor integrated circuit (IC) device, more particularly, to a semiconductor IC device including an information storing circuit using blown and unblown fuses for uses in a random access memory (RAM) device.
In a RAM device, a large number of memory cells are arranged along rows and columns. The density of defects generated in such a semiconductor memory device during the manufacture thereof is relatively independent of the integration density of the device. Rather, it derives from the semiconductor manufacturing technology. In general, the higher the integration density of the device, the greater the ratio of normal memory cells to defective memory cells. This is one of the advantages of increasing the integration density of a semiconductor memory device.
Even if a device includes only one defective memory cell, however, the device cannot be operated normally and, therefore, must be scrapped. As a result, despite the lower ratio of defective memory cells, greater integration density means reduced manufacturing yield.
To overcome the problem of defective memory cells, use is made of redundancy memory cells. When a defective memory cell is detected at the last stage of its manufacturing process by testing, it is electrically replaced by the redundancy memory cell. The replacement is effected for each row or column rather than each cell so that a redundancy memory cell row or column is selected instead of the memory cell row or column including the defective memory cell. In general, one or two redundancy memory cell rows or columns are usually provided.
In such a redundancy configuration, in order to store address information of such a defective row or column and to disable regular decoders for selecting normal memory cells so as to select the redundancy row or column in response to an address of the defective row or column, a redundancy control circuit is provided. A redundancy control circuit includes fuse-type read-only memories (ROM's) each having an information storing circuit.
A unit information storing circuit in prior art devices incorporates one fuse for each one bit of information to be stored (e.g., Electronics, July 28, 1981, p. 129 and p. 123). Therefore, the information storing circuit stores date "1" or "0" by a blown fuse or an unblown fuse. For example, upon completion of the major part of the manufacturing process of the device, and in the succeeding testing process wherein the defective rows or columns are detected and the writing data is determined, when writing data "1", a polycrystalline silicon fuse is blown by electrical programming or laser programming. However, as will be explained later in more detail, there is a relatively large probability of recovery of a polycrystalline silicon fuse from the blown to unblown state during the operation of the device, due to the particularities of the blowing phenomenon and the non-uniformity of shape of the blown fuse. For example, after blowing, the gap in the fuse establishing the disconnected state is often small (several 100 .ANG.). The high voltage applied thereto creates a strong electric field which causes a slow "flow" of the conductive material. This eventually can cause a short-circuited state, i.e., an unblown state. Accordingly, there is also a relatively large probability of change of data stored in the information storing circuit from "1" to "0", thereby reducing the reliability of the information storing circuit.